Pillars,
not headlines.
Tech moves too fast for daily news to mean anything. We organize what matters into long-running, continuously-updated topic hubs — and let the headline churn happen at the edges.
The AI memory bottleneck.
The constraint that's quietly reshaping the trillion-dollar AI compute build-out — explained, tracked, and updated as it evolves. Six solution paths, four still unresolved.
What I'm following.
The advanced packaging race
CoWoS, EMIB, SoIC. Why the assembly line became the new fab.
Export controls & the new silicon geopolitics
The expanding chokepoints between the US, China, and the supply chain in the middle.
The power wall
Data centers vs. the grid: where AI's electricity actually comes from.
The post-cloud cloud
Neoclouds, sovereign clouds, and the unraveling of the AWS/GCP/Azure trio.
The model-weight perimeter
Securing what's now the most valuable IP on the planet — and failing to.
Long-form, this week.
Samsung's HBM3E qualification, finally. The full timeline and what it means for NVIDIA's 2026 allocation strategy.
For 18 months Samsung was the third HBM vendor on paper only. NVIDIA's quiet May qualification changes everything — including SK Hynix's pricing power and Micron's growth ceiling.
The hyperscalers built nuclear deals nobody can finance. Here's what happens when reality hits.
SMR contracts announced in 2024 and 2025 looked clean. The capex curves don't pencil out, and three of seven announced deals are quietly behind. Source-by-source breakdown.
Commerce's HBM3E export guidance is narrower than reported. The HBM4 ambiguity is the real story.
Reading the actual rule text — not the headlines — reveals three exemptions and one critical omission. We walk through every line that matters.
Why every AI training run is now a packaging negotiation.
The bottleneck no longer measured in GPUs but in CoWoS slots. How TSMC quietly became the gatekeeper of the entire frontier-AI roadmap — and what the 2027 packaging map looks like.
Cerebras WSE-4 is generally available. We ran the benchmarks. The numbers are real.
Wafer-scale inference has spent four years as a press release. With WSE-4 in our hands, the latency-vs-cost economics finally pencil out for a specific, narrow class of workloads.
The essay shelf.
The hyperscalers built nuclear deals nobody can finance. Here's what happens when reality hits.
SMR contracts announced in 2024 and 2025 looked clean. The capex curves don't pencil out, and three of seven announced deals are quietly behind. Source-by-source breakdown.
↳ AI · MemoryWhy every AI training run is now a packaging negotiation.
The bottleneck no longer measured in GPUs but in CoWoS slots. How TSMC quietly became the gatekeeper of the entire frontier-AI roadmap — and what the 2027 packaging map looks like.