Why every AI training run is now a packaging negotiation.

For the first eighteen months of the generative-AI boom, the question that mattered for every frontier lab was: how many GPUs can you get? By late 2025, the question quietly changed. It is now: how many CoWoS slots has TSMC committed to your supplier?

This is not a semantic shift. It is the difference between a market where compute is the constraint and a market where assembly is — and they behave nothing alike. GPUs can be allocated in software; packaging cannot. GPUs can be virtualized across regions; packaging cannot. GPUs come off a wafer in the thousands; CoWoS-L finished modules come off TSMC's advanced packaging line in the dozens per week. Every frontier model now in training was, eighteen months earlier, a packaging-slot negotiation.

Setup: what we mean by "the packaging line."

Modern AI accelerators are not single chips. An NVIDIA H200 is a system: one GPU compute die fabricated on TSMC's N4 process, six high-bandwidth-memory (HBM) stacks fabricated by SK Hynix (or Micron, or Samsung), and a silicon interposer that wires them all together with thousands of micron-scale traces. Assembly is what binds them — and assembly is what's hard.

TSMC's CoWoS family — Chip-on-Wafer-on-Substrate — is the de facto standard. CoWoS-S handles older designs; CoWoS-L is what every leading-edge GPU uses today. Each CoWoS-L unit requires three weeks of process time on machinery that, as of mid-2026, exists in roughly four buildings on Earth — three in Taiwan, one in Arizona. SemiAnalysis estimates [3] CoWoS-L finished-module output at approximately 480,000 units per quarter, against demand approaching 1.4 million.

Foundry capacity is plentiful. The wafer side is fine. The problem is the back end. We could buy every wafer we needed and still have nowhere to put the HBM.— Senior procurement lead, top-five hyperscaler · Mar 2026

The CoWoS chokepoint.

The packaging shortage is structural, not cyclical. Building a CoWoS line is not the same problem as building a fab — it's a different problem, and in some ways a harder one. The equipment is heterogeneous (lithography, plating, grinding, bonding), the process is yield-sensitive at every step, and the qualification gates for each GPU/HBM combination are independent. TSMC cannot simply "add capacity" the way one would add a foundry shift. Every new CoWoS line is a 14- to 22-month build, and yields ramp slowly.

What a "slot" actually buys you.

A CoWoS slot is not a unit of GPU output. It is a unit of finished package — interposer, GPU die, HBM stacks, and substrate, qualified together. Slots are negotiated quarters in advance, with HBM allocation locked at the same time. NVIDIA, AMD, and the hyperscaler ASIC programs do not buy packaging on the spot market; the spot market doesn't meaningfully exist.

• Lead time One CoWoS-L slot, from order to finished package, is currently quoted at 52 weeks. Three years ago it was 16.
• Allocation ~62% of all 2026 CoWoS-L output is already pre-allocated to NVIDIA. AMD takes another ~14%. Hyperscaler ASICs take ~18%.
• Spot The remaining ~6% is "merchant" capacity — and it's not really merchant, it's strategic optionality TSMC holds back.

An auction in everything but name.

Inside this constrained system, allocation has come to resemble an auction — not in TSMC's pricing, which remains famously stable, but in the structure of side deals around it. We've documented three patterns over the last twelve months, drawn from interviews with seven people on the procurement side at hyperscalers and frontier labs.

First, pre-payments. Several frontier labs have pre-paid 6–18 months of accelerator orders in cash, with the explicit purpose of letting their cloud partner secure packaging-slot priority. The cash never touches TSMC directly; it lubricates the chain just enough.

Second, capacity swaps. Two hyperscalers — names withheld — have entered private agreements to trade GPU allocation across regions in exchange for HBM allocation flexibility. This is novel; eighteen months ago, it would have been considered competitively unthinkable.

Third, vertical lock-in. The most consequential pattern: HBM vendors are increasingly co-locating capacity decisions with specific GPU customers. SK Hynix's HBM3E and HBM4 ramps are visibly tilted toward NVIDIA. Micron's are tilted toward Microsoft. Samsung, now finally qualified, is the marginal supplier — and is being courted by both AWS and Meta in ways neither company wants reported.

Who gets stranded.

The clearest losers are the second-tier accelerator startups. Their roadmaps assumed merchant-market access to HBM and CoWoS — capacity that, for any practical 2026–27 program, no longer exists. Multiple Series-C and -D AI hardware companies have privately told investors their 2027 product depends on capacity commitments they do not yet have. The Information reported [9] on three such companies in March; we've identified at least four more.

The second-tier hyperscalers face a different version of the same problem. Oracle, IBM Cloud, and several sovereign-cloud programs are competing for what is effectively NVIDIA's "long tail" of allocation — capacity that NVIDIA itself is increasingly directing toward customers who can guarantee multi-year offtake. The neoclouds — CoreWeave, Lambda, Crusoe — are interesting test cases. They were structurally over-allocated in 2024; that lead has compressed faster than expected.

2027 implications.

Three things follow from where we are. First, packaging — not memory, not compute — is the variable to watch through the rest of 2026. TSMC's capex commentary on quarterly calls is now more material than NVIDIA's GPU shipment commentary, because the latter is downstream of the former. Second, the second-source story for advanced packaging is finally real. Samsung's external packaging program is signing customers; Intel Foundry's is too. Both ramps are slow, but the trajectory has changed. Third, custom-silicon programs at hyperscalers are not, on average, going to escape this constraint — they sit on the same CoWoS line. The exceptions are designs that deliberately use older packaging (CoWoS-S) or non-CoWoS alternatives (Intel EMIB-T, Samsung I-Cube).

The throughline, for readers of this pillar: capacity capability is the new compute capability. The companies that win the next eighteen months will be the ones that locked their packaging in twelve months ago. Read the pillar overview for the full landscape, or jump to the six solutions tracker to see how that capability is being built.