Inside TSMC's CoWoS expansion plan, and why HBM supply still won't catch up.

TSMC CEO C.C. Wei told analysts in July 2026 that packaging capacity is so tight it now limits customer growth. The statement crystallized what supply-chain data had been signaling for months: even as high-bandwidth memory production ramps across three qualified vendors, the assembly step that bonds HBM stacks to GPU dies has become the binding constraint on AI accelerator shipments. CoWoS lead times stood at 52 to 78 weeks as of August 2026, meaning orders placed today won't ship until mid-2028, according to Silicon Analysts.

TSMC is targeting 120,000 wafers per month of CoWoS capacity by the fourth quarter of 2026, double the end-2024 baseline, Silicon Analysts reported in August. Morgan Stanley projects the foundry will reach 200,000 wafers per month in 2027, supported by capital expenditure forecasts of $56 billion in 2026 and $75 billion in 2027, according to 404k Research. That expansion still leaves a structural gap: Morgan Stanley estimates 2027 demand at 136,000 wafers annually for Nvidia alone, with AMD claiming 55,000, Broadcom 52,000, and AWS 15,000. The arithmetic implies allocation pressure will persist through at least the first half of 2027.

Why packaging became the new fab

CoWoS (Chip-on-Wafer-on-Substrate) is TSMC's heterogeneous integration platform that places GPU dies and HBM memory stacks side-by-side on a silicon interposer, then mounts the assembly onto an organic substrate. The interposer provides microbump interconnects with pitches measured in single-digit micrometers, enabling the bandwidth density required for modern AI accelerators. Third-generation CoWoS entered volume production in 2026 and supports up to 12 HBM chips per package, WinBuzzer reported from TSMC's May symposium in Hsinchu. A 14-reticle platform capable of integrating 20 HBM stacks is mapped to 2028.

TSMC Vice President for Business Development Yuan Li-pen told the symposium that the 5.5-reticle-size CoWoS technology has achieved yields exceeding 98 percent. High yield reduces the economic penalty of large interposers but does not eliminate the throughput ceiling imposed by tool count and cycle time. Each CoWoS package requires wafer thinning, die placement with sub-micron alignment tolerance, mass reflow for microbump formation, underfill dispensing, and substrate attach. The process is serial and tool-intensive, unlike wafer fabrication where a single stepper can expose dozens of reticles per hour.

TSMC allocates 10 to 20 percent of its annual capital expenditure to advanced packaging, testing, mask making, and related infrastructure, compared with 70 to 80 percent for process technology, Inside Deep Tech reported. The smaller base means that an 80 percent compound annual growth rate for CoWoS and SoIC capacity through 2027, as TSMC projected at the May symposium, still leaves absolute capacity trailing demand. Absolute Digital Publishers noted that percentage growth rates obscure the base-size gap: packaging capacity started 2026 far smaller relative to demand than wafer capacity, so faster growth still leaves it behind in absolute terms.

HBM supply clears, packaging does not

All three major HBM vendors now ship HBM4 in volume. SK Hynix began mass production in late 2025, Samsung and Micron followed in the third and fourth quarters of 2026. Silicon Analysts reported in August that the qualification bottleneck has shifted fully to packaging, with CoWoS allocation now the binding constraint on system availability rather than HBM supply. This represents a structural change from 2024 and early 2025, when HBM3E yield issues at Samsung and capacity limits at SK Hynix created memory shortages that masked packaging constraints.

The shift is visible in lead-time data. CoWoS orders placed in August 2026 carried delivery windows of 52 to 78 weeks, extending beyond 12 months for the first time in the platform's history, according to Silicon Analysts. Midas Analytics estimated a 20 percent supply-demand gap for 2026 and confirmed the 52 to 78 week lead-time range. TSMC Chairman C.C. Wei told the June 2026 shareholders' meeting that 2026's planned production of AI accelerator chips using CoWoS was fully sold out.

High-performance computing accounted for 66 percent of TSMC's second-quarter 2026 revenue, Inside Deep Tech reported, underscoring the revenue concentration risk that packaging constraints impose on the foundry's growth trajectory. The allocation pressure has forced TSMC to explore outsourcing options that would have been unthinkable two years ago.

Outsourcing to a rival

TSMC is redirecting a portion of CoWoS back-end assembly to Intel's facility in Penang, Malaysia, according to Seoul Economic Daily, which cited Taiwan Economic Daily News export data showing $1.3 billion in HBM shipments to the Intel site. The arrangement is notable because Intel operates its own competing advanced-packaging platforms (EMIB, Foveros) and remains a direct rival in process technology. Wei acknowledged the outsourcing strategy during the July earnings call, stating that TSMC welcomes additional flexibility in the market because it helps the company's front-end wafer business, Inside Deep Tech reported.

Intel's Penang facility is the only outsourced assembly and test (OSAT) site with the scale and cleanroom infrastructure required for HBM integration, according to Seoul Economic Daily. Traditional OSAT providers lack the capital equipment and process control needed for sub-10-micrometer microbump placement and the thermal management required during mass reflow of packages containing multiple HBM stacks. Midas Analytics noted that the OSAT outsourcing strategy reflects the severity of the capacity shortfall, as TSMC typically retains advanced packaging in-house to protect process learning and customer relationships.

The 2027 inflection

Morgan Stanley's 200,000-wafer-per-month forecast for 2027 implies TSMC will add 80,000 wafers per month of incremental capacity during the year, a step-change from the 60,000-wafer addition projected for 2026. The $75 billion capital expenditure estimate for 2027, up from $56 billion in 2026, suggests TSMC is front-loading investment to close the gap, according to 404k Research.

At 200,000 wafers per month, allocation discipline will remain necessary. Morgan Stanley's demand breakdown for 2027 totals 258,000 wafers annually across Nvidia, AMD, Broadcom, and AWS alone, implying a utilization rate above 85 percent before accounting for other customers such as Google TPU or additional cloud service providers. The model assumes Nvidia will consume 136,000 wafers, AMD 55,000, Broadcom 52,000, and AWS 15,000, according to 404k Research. Lead times are unlikely to compress below six months until the second half of 2027.

TSMC's glass-substrate roadmap, branded CoPoS (Chip-on-Panel-on-Substrate), remains on a longer timeline. Wei told analysts in July 2026 that the pilot line is operational but volume production will require about another year, Inside Deep Tech reported. Glass substrates offer lower thermal expansion coefficients and better high-frequency signal integrity than organic substrates, but the manufacturing process requires through-glass via formation, defect-free metallization, and multi-layer redistribution layer alignment with tolerances tighter than current lithography can reliably achieve at panel scale. The technology will not contribute meaningful capacity before 2028.

Implications for system builders

The packaging bottleneck imposes a hard ceiling on AI accelerator shipments regardless of wafer supply or HBM availability. Hyperscalers with long-term CoWoS allocations secured in 2024 and early 2025 will receive priority, while newer entrants face 18-month lead times that make capacity planning nearly impossible. Absolute Digital Publishers noted that the supply-demand imbalance creates structural pricing power for TSMC and its anchor customers, as secondary-market GPU availability remains constrained even as HBM spot prices stabilize.

The constraint also explains why TSMC's gross margins have remained elevated despite increased competition in advanced nodes. Packaging represents a choke point where the foundry faces no credible near-term competition at the required scale and complexity. Samsung's I-Cube platform and Intel's EMIB remain subscale relative to CoWoS, and neither has demonstrated the yield or throughput needed to absorb spillover demand. The result is a market structure where TSMC can maintain pricing discipline even as it outsources incremental volume to Intel, because the alternative for customers is no capacity at all.